The present invention relates to a method for manufacturing a semiconductor device. More particularly, the present invention relates to a method for manufacturing a semiconductor device which comprises the step of burying a relatively thick insulating film in the field region so as to make its upper surface substantially flush with the upper surface of a semiconductor substrate.
In a semiconductor device, particularly an MOS type semiconductor device, which uses a silicon substrate, forming a thick oxide film in the region between elements, what is called a "field region", is generally carried out in order to eliminate the deterioration of insulation due to the production of a parasitic channel and at the same time, to reduce the parasitic capacity.
In the prior art, a selective oxidation method is well known as such thick oxide film-forming method. This method involves oxidizing at high temperature a wafer prepared by coating an element formation region with an oxidation-resistive mask, typically with a silicon nitride film, thereby selectively forming a thick oxide film in the field region. According to this selective oxidation method, however, during the oxidation the field oxide film eats into the element formation region from an end portion of the silicon nitride film in the form of a bird's beak. As a consequence, one substantial element dimension is decreased, which impairs the high integration of an integrated circuit. Further, according to the selective oxidation method, after the formation of the field oxide film, a step difference equal to approximately half the thickness of the field oxide film is produced between the field region and the element formation region. Since this step difference remains until the succeeding steps are completed, it decreases the reliability of the resultant semiconductor device by causing a decrease in the precision of a succeeding lithography, a disconnection of a metal interconnection layer in the step difference, etc.
A method for forming the field oxide film is known which is capable of removing the formation of the abovementioned bird's beak and preventing the production of the step difference between the field region and the element formation region. This method is described in, for example, Japanese Patent Application No. 56-55450. This method will be explained briefly with reference to FIGS. 1A to 1F.
First, as shown in FIG. 1A, for example, an oxide film 12 and then an aluminum mask thereon are formed on a p-type silicon substrate 11 by an ordinary photolithography technique. The reference numeral 14 denotes a resist mask used for patterning the oxide film 12 and the aluminum mask 13. Next, after removal of the resist mask 14, as shown in FIG. 1B, the silicon substrate 11 in the field region is etched, using the aluminum mask 13 as a mask, to a depth substantially equal to the thickness of a predetermined field oxide film, thereby forming grooves. Subsequently, an impurity of the same conductivity as that of the substrate 11, for example, boron, is ion-implanted in those grooves, thereby forming an ion-implanted region 15.
Thereafter, as shown in FIG. 1C, a SiO.sub.2 film 16a is deposited on the whole surface of the resultant structure by, for example, a plasma CVD method. Next, when etching is carried out for about one minute using, for example, ammonium fluoride solution, since the etching rate for the edge portions of the plasma CVD SiO.sub.2 film 16a is five to twenty times as high as that for the flat portions, the edge portions of the SiO.sub.2 film 16a located at the step difference portions are selectively etched, with the result that the SiO.sub.2 film 16a is disconnected at each portion of step difference, whereby the side face of the aluminum mask 13 is exposed. When, thereafter, the aluminum mask 13 is removed by etching, the portions of the plasma CVD SiO.sub.2 film deposited on the aluminum mask 13 are lifted off together with the aluminum mask. Thus, as shown in FIG. 1D, the CVD SiO.sub.2 film 16a is buried only in the field region. At this time, as shown in FIG. 1D, fine grooves are formed between the field region and the element formation region.
Next, as shown in FIG. 1E, the CVD SiO.sub.2 film 16b is deposited on the entire surface of the resultant structure. Recesses corresponding to the fine grooves are formed on the surface of this CVD SiO.sub.2 film 16b. Thereafter, a flowable material film 17, the etching rate for which is equal to the etching rate for the CVD SiO.sub.2 film 16b, is coated on the CVD SiO.sub.2 film 16b, thereby permitting said flowable material film 17 to be introduced into said recesses and bury them, thus permitting the resultant structure to have a flat surface. Thereafter, the flowable material film 17 and the CVD SiO.sub.2 film 16b are etched uniformly over the entire surface of the resultant structure in the order mentioned. As shown in FIG. 1F, the surface of the silicon substrate 11 corresponding to the element formation region is thus exposed. At this time, the field region is kept buried within the SiO.sub.2 film 16 on a substantially flat basis. Thereafter, predetermined elements are formed by the ordinary method, in the element formation region.
The above-mentioned prior art method, however, has the following drawbacks. In the prior art method, after etching the substrate using the aluminum mask 13, this mask must be left as a lift-off material for a succeeding lift-off step. For this reason, the surface of the etched substrate is contaminated by aluminum. Prior to forming the CVD SiO.sub.2 film on the substrate, the substrate surface is conventionally treated with acid to stabilize the interfacial property. However, the above-mentioned prior art method makes it impossible to effect the acid treatment due to the existence of the aluminum mask 13. Instead, in the prior art, the substrate surface is washed by an organic solvent, which fails to sufficiently wash the substrate surface. Further, while the CVD SiO.sub.2 film is usually formed on the substrate through the thermal oxide film for the purpose of stabilizing the interfacial property, the above-mentioned prior art method does not permit the formation of the thermal oxide film due to the existance of the aluminum mask 13. This makes it necessary to deposit the plasma CVD SiO.sub.2 film 16a directly onto the etched silicon substrate. For the above-mentioned reasons, the prior art method results in the interfacial property of the field region becoming unstable.
Furthermore, according to the prior art method, it is impossible to obtain, with high reproducibility, the discontinuity of the CVD SiO.sub.2 film 16a at the portions of step difference by selective etching. For this reason, in some cases, it is impossible to carry out the lift-off step.
The problems inherent in the prior art method, as mentioned above, have undesirable effects upon the characteristics of the element formed in a succeeding step, and thus decrease the reliability and yield of the resulting integrated circuit.